Shenzhen V-STAR Industry & Trade Co.,LTD.--Professional Supplier of LAUFFER Lamination System
From PCB to IC carrier board
2022-05-17 15:59
SAP, mSAP, SLP-look at the technology we use now, the acronyms are crazy! In terms of consumer electronics, the smartphones you keep on hand every day, or at least the PCBs installed in the next generation of smartphones, will be manufactured using mSAP technology. Current PCB design and manufacturing is completely dependent on the technology applied.
Standard subtractive etching has been used in the PCB industry. The continuous development of materials, chemicals and equipment has enabled traditional PCB manufacturing processes to achieve line width and line spacing of 30 μm and other feature sizes. At present, large factories with complex process production capacity are developing the latest technology. The line width and line pitch produced by the mainstream PCB manufacturing process can only reach 50 μm to 75 μm. The development of the electronics industry is very rapid, the industry's requirements for the complexity of electronic products are getting higher and higher, PCB design traces are getting thinner and thinner, the materials used are getting thinner and thinner, and the size of the vias is getting smaller and smaller. The traditional development process is to first shift to HDI technology using micro vias and multiple lamination cycles in the manufacturing process. Today's mSAP and SAP technologies provide us with more advanced methods, because with this technology we can produce line widths and line pitches of less than 25 μm and meet extremely complex design requirements.
First clear the definition of a few terms
· Subtractive etching method: usually used in the production of printed circuit boards. The process begins with a copper-clad laminate, which is coated with a film and then etched (etching away the copper) to form the wiring.
-additive PCB manufacturing: This process uses additive rather than subtractive methods to form wiring
-SAP: semi-additive method, using IC production method
· mSAP: Modified semi-additive process with IC production method
· SLP: carrier-like PCB; PCB produced using mSAP or SAP technology (rather than subtractive etching)
SAP and mSAP are commonly used processes in the production of IC carrier boards. As PCB production adopts and integrates this technology, the technology is expected to fill the gap between IC manufacturing capabilities and PCB manufacturing capabilities. Subtractive etching has limitations in producing thinner line widths/pitches, while IC production is limited by small size. After PCB manufacturing adopts SAP and mSAP processes, it can have the opportunity to produce line widths and line pitches of less than 25 μm on larger-sized boards.
In the PCB production process, the SAP and mSAP processes start with the inner core medium and the thin copper layer. One fundamental difference between the two processes is the thickness of the seed copper layer. In general, the SAP process starts with a thin electroless copper coating (less than 1.5mm), while the mSAP starts with a thin laminated copper foil (greater than 1.5mm). There are many ways to implement this technology, which can be selected based on production requirements, cost, required capital investment and R & D process capabilities.
Process
The processes used for SAP and mSAP are similar. The substrate is first coated with a thin copper layer. This is followed by a negative pattern design, followed by electroplating with a copper layer of the desired thickness, after which the seed copper layer is removed. In order to further understand the process steps of PCB addition, I had an in-depth exchange on this topic with Mike Vinson, president and CTO of Averatek. Averatek, based in California, is a company specializing in the production of catalytic inks, which can complete the additive process. He shared Averatek IP technology information and personal insights. Averatek's atomic layer deposition (ALD) parent inks can be used for small batch sample production or high-volume mass production applications, both fully additive and semi-additive. The catalytic ink controls the horizontal dimension of the line width and pitch, while the additive process only deposits metal on the photoresist-defined pattern, thereby controlling the vertical dimension of the metal thickness.
The Averatek process consists of six basic steps:
1. Drill vias in the substrate using mechanical drilling or laser drilling. (Hint: If the customer's process requires drilling after the Averatek process is completed or does not require drilling through holes, then this step is optional.)
2. The substrate is then prepared for subsequent processing. In most cases, this step is a simple cleaning and installation of the material in an appropriate handling system.
3. Coating the substrate with the Averatek ALD precursor catalytic ink and curing to form a sub-nanolayer of catalytic material (thickness <1nm).
4. Electroless copper is deposited onto the precursor. The copper layer thickness is between 0.1 µm and 1.0 µm.
5. Image the photoresist layer using photolithographic techniques to obtain a pattern on which the copper material can be deposited. The line width and distance generated at this time should be greater than 5 µm.
6. Finally, the circuit is formed by electrolytic copper plating, and then the residual resist is stripped and flash etching is performed.
This technology can produce very thin traces on flexible, rigid substrates or other materials, and the cost is very competitive. Because the holes are plated along the wiring, a smooth seamless transition can be achieved. Many applications that require thin wiring patterns support the transmission of high-speed, high-frequency signals, so the smoothness and quality of conductive metals are critical. The cross section of the conductor produced by the above process is circular, and the surface of the conductor is very smooth. These properties are very suitable for high-frequency lines because it can minimize crosstalk, short circuits and energy loss.
Source: The Electronic Age
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